VHDL-Forum

pouriapouria · Registrierter Benutzer Beiträge: 1

Sorry my German is not so good os I try in English

Hi there.

I'm trying to design a state machine to Run at 100 MHz in an Actel FPGA.

Most of my states have 6 or more exits.

My questions is how many exits can I have on one single state so that the Logic that is generated by the syntisizer dose not have a delay more then 10ns (100MHz clock).

How can I calculate this delay depending on number of exit from a single state in my state machine ???

Thank you so much for your help !!!