VHDL-Forum

kurapati · Registrierter Benutzer Beiträge: 1

Hi
I have some problem with writing FIFO. when two conditions are fullfilled at same clock to write the data to same FIFO. How can a give priority and write data one after the other to the same FIFO so that there will not be any loss of data even for many conditions.
thanks in advance
bye

Dr. Faustus · Administrator Beiträge: 107 Ort: Aßling

Hi,

it's not an easy task. If you solve it let me know.

Regards,

Michael

frodus · Gast

Hi,

usual the implementation of the fifo is based on a rd and wr ptr.
And there should be on procedure that puts data into the fifo and
one that reads data from the fifo.

If it is now the case that you need to put more then one element into the fifo
you can simply create a procedure that puts n elements into the fifo.

Note: Before you start the implementation consider all wrap around and overun criterias.

/frodus