VHDL-Forum

Dr. Faustus · Administrator Beiträge: 107

Hallö,

hier ein beispiel für eine einfache Testbench.
Die anpassungen für ein AND sollten nicht so schwer sein.

Gruesse.

-- **************************************************************
-- * Name : tb_c_a_code_gen.vhd *
-- * ---------------------------------------------------------- *
-- * Funktion : *
-- * ---------------------------------------------------------- *
-- * Autor : Dipl.-Ing.Michael Bodenbach *
-- * ---------------------------------------------------------- *
-- * Date : 06.10.2003 *
-- * Modified : *
-- * ---------------------------------------------------------- *
-- * Modifications : *
-- * *
-- **************************************************************

-- **************************************************************
-- * Libraray Declarations *
-- **************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- **************************************************************
-- * Entity declaration *
-- **************************************************************
entity testbench_01 is
end;

-- **************************************************************
-- * Begin of the architecture *
-- **************************************************************
architecture testbench_arch of testbench is

-- **************************************************************
-- * Test-Component declaration *
-- **************************************************************
signal clock : std_logic := '0';
signal c_a_code : std_logic;
signal gps_prn_sn : std_logic;
signal Reset : std_logic;

component c_a_code_gen
port (
clock : in std_logic; -- Generator clock
c_a_code : out std_logic;
gps_prn_sn : in std_logic;
Reset : in std_logic -- Reset
);
end component;

-- **************************************************************
-- * Define the system clock rate *
-- **************************************************************
CONSTANT SYS_CLK : Time := 977517 ps; -- 1.023MHz

signal count : std_logic_vector(3 downto 0);

begin

uut : c_a_code_gen port map (
clock => clock,
c_a_code => c_a_code,
gps_prn_sn => gps_prn_sn,
Reset => Reset
);

rst : process
begin
Reset <= '1';
wait for 10 ns;
Reset <= '0';
wait;
end process;

par : process(Reset, clock)
begin
if (Reset = '0') then
count <= (others => '0');
gps_prn_sn <= "1";
elsif rising_edge(clock) then
count <= count + 1;
if (count = x"a") then
gps_prn_sn <= not gps_prn_sn;
end if;
end if;
end process;

-- System Clock Generation
sysclk : process
begin
wait for SYS_CLK / 2;
clock <= not clock;
end process sysclk;

end testbench_arch;

configuration c_a_code_gen_cfg of testbench is
for testbench_arch
end for;
end c_a_code_gen_cfg;