Finot
Gast
|
Erstellt: 29.03.05, 17:34 Betreff: Kompilationsproblem
drucken
weiterempfehlen
|
|
|
Allo,
entschuldigung mich bitte, I spreche deutsch aber nicht so gut. Also werde ich in english schreiben...
I'm french and just began a University project, I must acquire data from a CMOS CCD sensor and put them in the FPGA memory.
I have big problems with compilation, because it's veeery long, and when it compiled (before I used the "loop" statement), I had problems with the licence:
"Warning: FLEXlm software error: Future license file format or misspelling in license file..."
Do you have advices for me to go back on the right path?
This is the code I use now:
LIBRARY ieee; Use iEEE.std_logic_1164.all; Use ieee.std_logic_arith.all;
ENTITY recup IS PORT( VSYNC : IN STD_LOGIC; PCLK : IN STD_LOGIC; HREF : IN STD_LOGIC; Y : IN STD_LOGIC_VECTOR (0 TO 7) ); END recup;
ARCHITECTURE archi OF recup IS TYPE Matrice is ARRAY (0 TO 639) of std_logic_vector(0 TO 7); SIGNAL data : Matrice; SIGNAL i : integer;
BEGIN PROCESS(PCLK) BEGIN
LOOP EXIT WHEN i=1;
IF (VSYNC'EVENT AND VSYNC='0') THEN IF (PCLK'EVENT AND PCLK='1') THEN IF HREF='1' THEN data(i)<=Y; i<=i+1; END IF; END IF; END IF;
END LOOP;
END PROCESS; END archi;
Danke schön.
|
|