VHDL-Forum

bladeexx · Erstellt: 24.05.07, 17:35 Betreff: Signal cannot be synthesized

Hi,

hab folgendes problem.

Habe diesen code geschrieben und kann den nicht synthetisieren.
Kann mir bitte jemand helfen?

architecture Behavioral of test_ent is
constant g_time:time:=3 ns;
constant delay_afect:time:=5 ns;
constant delay_signal:time:=1 ns;
constant delay_speedup:time:=2 ns;

begin
process(vict,afect) is
begin

victout<=transport vict after delay_signal;

if (vict='0' and afect ='1' and afect'event) then
victout<='1', vict after g_time;

elsif(vict='1' and afect='0' and afect'event) then
victout<='0', vict after g_time;

elsif(vict='1' and vict'event and afect='0' and afect'event) then
victout<= transport vict after delay_afect;

elsif(vict='0' and vict'event and afect='1' and afect'event) then
victout<= transport vict after delay_afect;

elsif(vict'event and vict='0' and afect'event and afect='0') then
victout<= transport vict after delay_speedup;

elsif(vict'event and vict='1' and afect'event and afect='1') then
victout<= transport vict after delay_speedup;

end if;
end process;
end Behavioral;