VHDL-Forum

burn77 · Registrierter Benutzer Beiträge: 4

Hi Sam,

I am not sure, if I can really help you. I tried to realize your comparator, but since I don't have the input of data_in, I just have realized some similar comparator...

greetings, burn

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_signed.all;
use ieee.numeric_std.all;

entity comparator is
port (
clk : in std_logic; -- clock signal
rst; -- reset signal
data_in : in std_logic_vector(14 downto 0);
correlation : out std_logic_vector(3 downto 0));
end comparator;

architecture behave of comparator is

constant sync_word : std_logic_vector (14 downto 0) := "001101011110001";
signal count : std_logic_vector(3 downto 0) := "0000";

shared variable: count1 : integer := 0;
signal clk1: std_logic := '0';
signal data_in1 : std_logic_vector(14 downto 0) := "001111111111111";

begin

clk1 <= not clk1 after 1 ns; -- I needed this since I don't have the inputs you have...

-- comparison process

process(clk1, data_in, rst)
begin
for i in 0 to 14
loop
if(data_in(i) = sync_word(i)) then
count1 <= count1 + 1;
end if;
end loop;
correlation <= std_logic_vector(to_unsigned(count1,4));
count := 0;
end process;
end behave;

I am not sure, if this will help you, but I hope so. Especially, it is important to use a variable for counting, I think, so you just have to transform the format into std_logic_vector, the instruction "to_unsigned" is within numeric_std.
All you have to realize is to connect the data_in with the internal signal data_in1 and you can compare any data_in with sync_word.

greetings, burn