VHDL-Forum

Marc10k · Neuling Beiträge: 7

Meine Vorfreude war vielleicht etwas zu früh. Den Fehler habe ich nicht mehr aber es werden leider auch meine Daten nicht mit der Clock übertragen. Ich den Code abgeändert und versucht die Daten im Takt der Clock zu übertragen. Nur leider klappt es nicht so wie ich mir das so vorstelle. Vielleicht kann jemand mir helfen.

Hier mein jetzige Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Header 7 bits 0010010
-- Data 1 24 bits 264744 - 0010.0110.0100.0111.0100.0100
-- Data 2 24 bits 199408 - 0001.1001.1001.0100.0000.1000
-- Checksum 4 bits

entity Sender is
Port ( Reset : in std_logic;
Run : in std_logic;
Mode : in std_logic_vector(1 downto 0);
clock : in std_logic;
Data : out std_logic);
end Sender;

architecture Behavioral of Sender is
begin

process (Mode, Run, clock)
variable shift_reg_h: std_logic_vector(6 downto 0);
variable shift_reg_d: std_logic_vector(23 downto 0);
variable shift_reg_c: std_logic_vector(3 downto 0);
variable M : integer;

begin
if (clock'event and clock = '1') then
if Run = '1' then
case Mode is
when "00" => -- good header, data segment 1 and checksum
-- send the header first
shift_reg_h := "0010010";
for I in 0 to 6 loop
shift_reg_h (6 downto 1) := shift_reg_h (5 downto 0);
if (clock'event and clock = '0') then
Data <= shift_reg_h (6);
end if;
end loop;
-- send the datasegment next
shift_reg_d := "001001100100011101000100"; --Marcus number
for I in 0 to 23 loop
shift_reg_d (23 downto 1) := shift_reg_d (22 downto 0);
Data <= shift_reg_d (23);
end loop;
-- send the checksum last

when "01" => -- good header, data segment 2 and checksum
-- send the header first
shift_reg_h := "0010010";
for I in 0 to 6 loop
shift_reg_h (6 downto 1) := shift_reg_h (5 downto 0);
Data <= shift_reg_h (6);
end loop;
-- send the datasegment last
shift_reg_d := "000110011001010000001000"; -- Johns number
for I in 0 to 23 loop
shift_reg_d (23 downto 1) := shift_reg_d (22 downto 0);
Data <= shift_reg_d (23);
end loop;
-- send the checksum last

when "10" => -- invalid header, data segment 1, checksum
-- send the invalid header first
shift_reg_h := "0000000"; -- INVALID HEADER
for I in 0 to 6 loop
shift_reg_h (6 downto 1) := shift_reg_h (5 downto 0);
Data <= shift_reg_h (6);
end loop;
-- send the datasegment last
shift_reg_d := "001001100100011101000100"; --Marcus number
for I in 0 to 23 loop
shift_reg_d (23 downto 1) := shift_reg_d (22 downto 0);
Data <= shift_reg_d (23);
end loop;
-- send the checksum last

when "11" => -- good header, datasegment 2, invalid checksum
-- send the header first
shift_reg_h := "0010010";
for I in 0 to 6 loop
shift_reg_h (6 downto 1) := shift_reg_h (5 downto 0);
Data <= shift_reg_h (6);
end loop;
-- send the datasegment next
shift_reg_d := "000110011001010000001000"; -- Johns number
for I in 0 to 23 loop
shift_reg_d (23 downto 1) := shift_reg_d (22 downto 0);
Data <= shift_reg_d (23);
end loop;
-- send the checksum last (INVALID)

when others =>
Data <= 'X';
end case;
end if;
end if;
end process;
end Behavioral;

Anbei auch noch mal der Code als vhd Datei.