VHDL-Forum

s_rowse · Registrierter Benutzer Beiträge: 2

Hallo,

Es tut mir leid, aber ich habe Deutsch seit einem langem Zeit nicht gesprochen, und ich kann keine Englisches VHDL forum finden. Ich brauch hilfe mit meinem parallel Komparator. Und leider jetzt muss ich auf Englisch sprechen...
I would be really appreciative if anyone could answer my post even though i've had to write in english to get my point across!

I'm having trouble getting my comparator to work. The idea is: the comparator compares two 15 bit sequences, and tallies up how many bits in the sequences have the same position and value. the number of bits that match is called the correlation value. for example
"1111" and "1111" have a correlation of 4
"0011" and "1100" have a correlation of 0, etc.

I tried making a for loop to do this. I then tested it by seeing what happened when two exactly the same sequences were compared over and over. instead of outputting a correlation value of "1111" (15) over and over, i found that it starts at 0 and counts from 0 to 15 by ones, which is not what it's supposed to do!

I have pasted my code below, there's not much. If you can give me some tips so i can fix it that would be fantastic!
Thankyou!
Sam

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity comparator is
port (
clk : in std_logic; -- clock signal
rst; -- reset signal
data_in : in std_logic_vector(14 downto 0);
correlation : out std_logic_vector(3 downto 0));
end comparator;

architecture behave of comparator is

constant sync_word : std_logic_vector (14 downto 0) := "001101011110001";
signal count : std_logic_vector(3 downto 0) := "0000";

begin

-- comparison process

process(clk, data_in, rst)
begin
for i in 0 to 14
loop
if(data_in(i) = sync_word(i)) then
count <= count + "0001";
else count <= count;
end if;
end loop;
correlation <= count;
end process;
end behave;

burn77 · Registrierter Benutzer Beiträge: 4

Hi Sam,

I am not sure, if I can really help you. I tried to realize your comparator, but since I don't have the input of data_in, I just have realized some similar comparator...

greetings, burn

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_signed.all;
use ieee.numeric_std.all;

entity comparator is
port (
clk : in std_logic; -- clock signal
rst; -- reset signal
data_in : in std_logic_vector(14 downto 0);
correlation : out std_logic_vector(3 downto 0));
end comparator;

architecture behave of comparator is

constant sync_word : std_logic_vector (14 downto 0) := "001101011110001";
signal count : std_logic_vector(3 downto 0) := "0000";

shared variable: count1 : integer := 0;
signal clk1: std_logic := '0';
signal data_in1 : std_logic_vector(14 downto 0) := "001111111111111";

begin

clk1 <= not clk1 after 1 ns; -- I needed this since I don't have the inputs you have...

-- comparison process

process(clk1, data_in, rst)
begin
for i in 0 to 14
loop
if(data_in(i) = sync_word(i)) then
count1 <= count1 + 1;
end if;
end loop;
correlation <= std_logic_vector(to_unsigned(count1,4));
count := 0;
end process;
end behave;

I am not sure, if this will help you, but I hope so. Especially, it is important to use a variable for counting, I think, so you just have to transform the format into std_logic_vector, the instruction "to_unsigned" is within numeric_std.
All you have to realize is to connect the data_in with the internal signal data_in1 and you can compare any data_in with sync_word.

greetings, burn

s_rowse · Registrierter Benutzer Beiträge: 2

Ich probiere auf Deutsch zu schreiben...
Vielen Dank! Ich hatte keine Ahnung, dass ich ein 'variable' benutzen mussten. Meinen Freund hat mir dass gerade jetzt gesagt

also, man muss IEEE.STD_LOGIC_ARITH.ALL benutzen.
Thankyou so much for replying even though i wrote mostly in English!

here is a copy of the working version for anyone else who is interested :-)

-------------------------------------------------------------------------------
-- Title : comparator
-------------------------------------------------------------------------------
-- Description : Compares the bits of two 15 bit sequence and keeps a tally
-- of how many of the 15 bits correlate.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
USE IEEE.STD_LOGIC_ARITH.ALL;

entity comparator is
port (
clk : in std_logic; -- clock signal
rst_ls : in std_logic; -- rst signals used
rst_ld : in std_logic;
data_in : in std_logic_vector(14 downto 0);
comparison : out std_logic_vector(3 downto 0));
end comparator;

architecture mix of comparator is

constant sync_word : std_logic_vector (14 downto 0) := "001101011110001";

begin

-- comparison process

process(data_in, rst_ls, rst_ld)
variable countValue : std_logic_vector(3 downto 0) := "0000";
begin

if(rst_ls = '0' or rst_ld = '0') then
countValue := "0000";
end if;

for i in 14 downto 0 loop
if(data_in(i) = sync_word(i)) then
countValue := countValue + 1;
end if;
end loop;

comparison <= countValue;
end process;

end mix;

xiaoou · Vielschreiber Beiträge: 53

Kllara · Stammgast Beiträge: 41

the number of bits that match is called the

thomas Li · Gast

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