VHDL-Forum

Johannes

Nachtrag hier mein Programm (Wo werden die Daten gespeichert die empfangen habe?

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity SerMod is
port (clk : in std_logic;
ClkSel : in std_logic;
Res : in std_logic;
TC : out std_logic;
OutClk16: out std_logic_vector(3 downto 0);
RxD : in std_logic;
TxD :out std_logic;
Test : out std_logic);
PD1 : out std_logic_vector (9 downto 0);
PD2 : out std_logic_vector (9 downto 0);
Mode : out std_logic_vector (1 downto 0);
end SerMod;

architecture BH of SerMod is
signal mclock : std_logic;
signal outbit : std_logic;
signal S_Count: std_logic_vector(8 downto 0);
signal S_Clock16x: std_logic_vector(3 downto 0);
signal S_Clock16x9: std_logic;
signal S_Count9: integer range 0 to 143;
signal S_Init:std_logic;
signal S_Nix:std_logic;
signal S_Nix1:std_logic;
-- signal S_Serin:std_logic;
constant C_TermCount: integer:=11;
constant C_TermCount9600: integer:=143;
begin

--S_Serin<=RxD;
ClockDivider: process(clk,S_Init)
begin
if(ClkSel='1') then

if(clk'event and clk='1') then
S_Nix <= not S_Nix;
if (S_Count >= "100011111") then
S_Count<="000000000";
else
S_Count<=S_Count + "000000001";
end if;
end if;

elsif (ClkSel='0') then

if(clk'event and clk='1') then
S_Nix1 <= not S_Nix1;
if (S_Count >= "000010111") then
S_Count<="000000000";
else
S_Count<=S_Count + "000000001";
end if;
end if;

end if;

if S_Init='0' then
S_Init<='1';

else
if S_Count>=C_TermCount then
S_Clock16x<=NOT S_Clock16x;
S_Count <="000000000";
else
S_Count<=S_Count+1;
end if;
S_Clock16x9<='1';
end if;
OutClk16<=S_Clock16x;
Test<=S_Nix and S_Nix1;
end process;

--ClockDivider9: process
--begin

-- wait until ((mclock'event and mclock='1') );
-- if S_Init='0' then
-- S_Init<='1';

-- else
-- if S_Count9>=C_TermCount9600 then
-- S_Clock16x<=NOT S_Clock16x;
-- S_Count9 <=0;
-- else
-- S_Count9<=S_Count9+1;
-- end if;
-- S_Clock16x<='1';
-- end if;
--end process;

TxD <= outbit;
-- Test<= S_Clock16x and S_Clock16x9;
end BH;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
------------------------------------
entity UART_RX is
port (
RESET: in std_logic; -- RESET
X16CLK: in std_logic; -- This clock is 16 time as fast as baud rate clock
DATA: out std_logic_vector(7 downto 0); -- The output on these signals is valid on the rising DATA_READY signal
SER_IN: in std_logic; -- Serial input line
DATA_READY: out std_logic -- This signal goes high one clock after DATA is valid. Signal is active for one clock.
);

end UART_RX;

architecture RX_UART_arch of UART_RX is

signal BUF: std_logic_vector(9 downto 0);

signal SER_IN1,SER_IN2: std_logic; -- These signals are used to double buffer a signal that is sources external to the board.
-- The double buffering syncs the signal to the on board clk.
signal Sample_counter: std_logic_vector(3 downto 0); -- There should be 16 X16CLK samples for each bit in the word.
signal bit_count : std_logic_vector(3 downto 0); -- This counts the bits in the word. 1 start, 8 data, and 1 stop.
signal VALID_DATA: std_logic; -- Valid data word flag.

type UART_STATE_TYPE is (IDLE,WAIT_ONE,WAIT_1ST_HALF,GET_DATA,WAIT_2ND_HALF,LAST_BIT);

signal UART_STATE: UART_STATE_TYPE; -- Where in the transmitted word are we?

begin

process(X16CLK,RESET)
begin
if RESET = '1' then
SER_IN1 <= '1';
SER_IN2 <= '1';
DATA <= "00000000";
DATA_READY <= '0';
elsif (X16CLK'event and X16CLK = '1') then
SER_IN1 <= SER_IN;
SER_IN2 <= SER_IN1;
DATA <= BUF(8 downto 1);
DATA_READY <= VALID_DATA;
end if;
end process;

Mode <= "0";

process (Mode)
begin

if Mode = '0' then
DB1 <= "0000000001";
DB1 <= "0000000000";
DB2 <= "0000000001";
DB2 <= "0000000000";
Mode <= "1"
DB1 <= "0010001000";
DB2 <= "0010001000";

end if;

end process;

process(X16CLK,RESET)
begin
if RESET = '1' then
UART_STATE <= IDLE;
bit_count <= "0000";
Sample_counter <= "0000";
BUF <= "1111111111";
VALID_DATA <= '0';
bit_count <= "0000";

elsif X16CLK'event and X16CLK = '1' then
case UART_STATE is
when IDLE => -- Waiting for Start Bit
if SER_IN2 = '0' then -- Start new bit and new word
UART_STATE <= WAIT_1ST_HALF;
else
UART_STATE <= IDLE;
end if;
Sample_counter <= "0001";
BUF <= "1111111111";
VALID_DATA <= '0';
bit_count <= "0000";
when WAIT_ONE => -- Start of new 16 sample bit
UART_STATE <= WAIT_1ST_HALF;
BUF <= BUF;
VALID_DATA <= '0';
bit_count <= bit_count;
Sample_counter <= "0001";
when WAIT_1ST_HALF => -- wait 8 samples of bit
if Sample_counter = "0111" then
UART_STATE <= GET_DATA;
else
UART_STATE <= WAIT_1ST_HALF;
end if;
Sample_counter <= Sample_counter + '1';
BUF <= BUF;
VALID_DATA <= '0';
bit_count <= bit_count;
when GET_DATA => -- get the ninth sample and call it good.
UART_STATE <= WAIT_2ND_HALF;
BUF <= SER_IN2 & BUF(9 downto 1);
Sample_counter <= Sample_counter + '1';
VALID_DATA <= '0';
bit_count <= bit_count;
when WAIT_2ND_HALF => -- wait the remaining samples.
if Sample_counter = "1110" then
UART_STATE <= LAST_BIT;
else
UART_STATE <= WAIT_2ND_HALF;
end if;
Sample_counter <= Sample_counter + '1';
BUF <= BUF;
VALID_DATA <= '0';
bit_count <= bit_count;
when LAST_BIT => -- Last sample in Bit
if bit_count = "1001" then -- Is it last bit in word?
UART_STATE <= IDLE;
bit_count <= "0000";
if BUF(9) = '1' and BUF(0) = '0' then
VALID_DATA <= '1';
else
VALID_DATA <= '0';
end if;
else
UART_STATE <= WAIT_ONE;
bit_count <= bit_count + '1';
VALID_DATA <= '0';
end if;

end case;
end if;
end process;

end RX_UART_arch;

------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity UART_TX is
port (
RESET: in std_logic; -- RESET
BAUDCLK: in std_logic; -- This clock is the BUAD rate clock
DATA: in std_logic_vector(7 downto 0); -- DATA to be sent
SER_OUT: out std_logic; -- Serial output line
SEND_DATA: in std_logic; -- Trigger serial out
BUSY: out std_logic -- Transmitting Flag
);

end UART_TX;

architecture TX_UART_arch of UART_TX is

signal BUF: std_logic_vector(9 downto 0);

signal count: integer range 0 to 9;

begin

process(BAUDCLK,RESET,BUF)
begin
if RESET = '1' then
count <= 9;
BUF <= "1111111111";
elsif BAUDCLK'event and BAUDCLK = '1' then
if count = 9 and SEND_DATA = '1' then -- Ready to send char
count <= 0;
BUF <= '1' & DATA & '0';
elsif count < 9 then -- cycle through word
BUF <= '1' & BUF(9 downto 1);
count <= count + 1 ;
else
BUF <= BUF;
count <= count;
end if;
end if;
end process;

BUSY <= '1' when count < 9 else '0';
SER_OUT <= BUF(0); -- Idle high

end TX_UART_arch;