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diego · Erstellt: 15.07.05, 19:11 Betreff: problem counter vhdl

hello,
I have a problem whit this code of counter

-- RR Generator
-- Specific Counter Module
-- Module of Counter : 8
-- VHDL Description code

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity countermod8 is
port(
ENABLE : in std_logic;
CLK : in std_logic;
RESET : in std_logic;
Y : out std_logic_vector(3 downto 0)
);
end countermod8;

architecture counter of countermod8 is
signal Z : std_logic_vector (3 downto 0);

begin
count_proc: process( clk, reset )
begin
if reset = '1' then
if ( enable = '1' ) then
Z <= ( others => '0' );
end if;
else
if clk'event and clk = '1' then
if ( enable = '1' ) then
if Z = "0111" then
Z <= ( others => '0' );
else
Z <= Z + 1;
end if;
else
Z <= Z;
end if;
end if;
end if;
end process;

end counter;

The error is at line " Z <= Z + 1; "
and wen i simulate whit modelsim thisi is a error:

No feasible entries for infix operator "+".
Type error resolving infix expression "+".

why???

thanks a lot Diego