VHDL-Forum

Unai · Gast

Hi all!!

We're having some problems with a finite-state machine in VHDL. When a button is pressed, it is supposed to go to its corresponding state, but the only thing we obtain in the simulation is that, if we press the BTN1 button, we go to the "0001" state, all right, but after that, if we press any other button, although button BTN1 is not pressed, the state machine goes to the "0001" state, ergo, the state of the BTN1 button. Here you have the source of the state machine:

architecture Behavioral of Maquina_Estados is
signal E: STD_LOGIC_VECTOR (3 downto 0):="0000";
signal ascii_cod: STD_LOGIC_VECTOR (7 downto 0);
begin
U: PROCESS (CLK, RST, BTN1, BTN2, BTN3, BTN4, BTN5, BTN6, BTN7)
BEGIN
IF (RST='1') then E<="0000";
ELSIF (rising_edge(CLK)) then
case (E) is

when "0000" => if (BTN7='1') then E <= "0111"; end if;
if (BTN6='1') then E <= "0110"; end if;
if (BTN5='1') then E <= "0101"; end if;
if (BTN4='1') then E <= "0100"; end if;
if (BTN3='1') then E <= "0011"; end if;
if (BTN2='1') then E <= "0010"; end if;
if (BTN1='1') then E <= "0001"; end if;

when "0001" => ascii_cod<= "01110111";
if TBE='1' then E <="1000"; end if;

when "0010" => ascii_cod<= "01110011";
if TBE='1' then E <="1000"; end if;

when "0011" => ascii_cod<= "00100000";
if TBE='1' then E <="1000"; end if;

when "0100" => ascii_cod<= "00011011";
if TBE='1' then E <="1000"; end if;

when "0101" => ascii_cod<= "01101101";
if TBE='1' then E <="1000"; end if;

when "0110" => ascii_cod<= "01100001";
if TBE='1' then E <="1000"; end if;

when "0111" => ascii_cod<= "01100100";
if TBE='1' then E <="1000"; end if;

when "1000" => E <="1001";

when "1001" => if TBE='1' then E <="0000"; end if;

when others => E <="0000";

end case;
end if;
END PROCESS U;

Hope you can help us.

P.S. We are using Xilinx ISE 11.4 Design Suite.

Thank you all!!