VHDL-Forum

kain · Gast

hi,everyone:
I am new to modelsim and vhdl this is a counter can clear and load, when I run the wave, it shows

run -all
# Break on sim:/count/ld
# Simulation stop requested.

but if I click run, it can pass

this is my code , thank you for your help

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity Count is
PORT(clr, m, cp, ld : IN STD_LOGIC;
input : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
output : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
Qcc: OUT STD_LOGIC);

end;

architecture behavioral of count is
signal curcout : STD_LOGIC_VECTOR(3 DOWNTO 0);
begin

process(clr, ld, cp, m)
BEGIN
IF(clr = '0')THEN
curcout <= "0000";
elsif(ld = '0')THEN
curcout <= input;
elsif (cp 'event and cp = '1' and m = '1')THEN
curcout <= curcout + "0001";
IF (curcout = "0000")THEN
Qcc <= '1';
ELSE
Qcc <= '0';
end if;
ELSIF (cp 'event and cp = '1' and m = '0')THEN
curcout <= curcout - "0001";
IF (curcout = "1111")THEN
Qcc <= '1';
ELSE
Qcc <= '0';
end if;
end if;
end process;
output <= curcout;
end behavioral;