VHDL-Forum

horvath · Erstellt: 15.04.11, 14:15 Betreff: signal_force problem

Hi,

I am facing the following problem with signal_force():
I use the following instantiation of the function, to deposit a down-counter to a smaller value, to speed up timing simulation:

signal_force (path_fpga_top & "u_0/inst_hfg_wdt/rst_ext_l_cnt_s", "10#11", 0 ns, deposit, open, 0);

I checked the wave. The counter gets the forced value(11), but after few clock cycles it gets back its original value(611). (I would expect, that it will count down from the new value)

I tries from Modelsim GUI to force the same signal at the same point in the simulation, an it worked. So it counted down from 11.

There is no way that tha counter is overwritten at an other place.

The question is, why does the signal gets back the original value after a few clk cycles if I use signal_force in the test bench?

Thank you for your help,
Andras