VHDL-Forum

Heikki · Erstellt: 06.10.04, 12:51 Betreff: Register will not synthetize...

Can anyone tell why this kind of 12-bit pipo register won't synthetize in ModelSim:

library ieee;
use ieee.std_logic_1164.all;

entity reg_12 is
port( input: in std_logic_vector( 11 downto 0);
sys_clk, reset, sample_rate: in std_logic;
output: out std_logic_vector( 11 downto 0));
end reg_12;

architecture RTL of reg_12 is

begin

p0: process(sys_clk, reset, sample_rate)

variable reg: std_logic_vector( 11 downto 0);

begin
if( reset = '1') then
reg := ( others => '0');
elsif rising_edge( sys_clk) then
if (sample_rate = '1') then
reg := input;
end if;
end if;

output <= reg;
end process p0;
end RTL;

ModelSim says: Error: Tried to use a synchronized value in call to '<=' and points to line:
output <= reg;

Thank you!