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Betreff |
Autor |
Datum |
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Re: Register will not synthetize...
I think, you just have to use a shared variable, I am not sure, but I think so. Hope, you have luck...
And you have to change the position of declaration of reg. Downwards, you can see it within the "=" lines
[quote]
Can anyone tell why this kind of 12-bit pipo register won't synthetize in ModelSim:
library ieee;
use ieee.std_logic_1164.all;
entity reg_12 is
port( input: in std_logic_vector( 11 downto 0);
sys_clk, reset, sample_rate: in std_logic;
output: out std_logic_vector( 11 downto 0));
end reg_12;
architecture RTL of reg_12 is
==============================================
shared variable reg: std_logic_vector( 11 downto 0);
==============================================
begin
p0: process(sys_clk, reset, sample_rate)
begin
if( reset = '1') then
reg := ( others => '0');
elsif rising_edge( sys_clk) then
if (sample_rate = '1') then
reg := input;
end if;
end if;
output <= reg;
end process p0;
end RTL;
ModelSim says: Error: Tried to use a synchronized value in call to '<=' and points to line:
output <= reg;
Thank you!
[/quote]
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burn77 |
06.10.04, 13:19 |
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Re: Comparator/Komparator
Hi Sam,
I am not sure, if I can really help you. I tried to realize your comparator, but since I don't have the input of data_in, I just have realized some similar comparator...
greetings, burn
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_signed.all;
use ieee.numeric_std.all;
entity comparator is
port (
clk : in std_logic; -- clock signal
rst; -- reset signal
data_in : in std_logic_vector(14 downto 0);
correlation : out std_logic_vector(3 downto 0));
end comparator;
architecture behave of comparator is
constant sync_word : std_logic_vector (14 downto 0) := "001101011110001";
signal count : std_logic_vector(3 downto 0) := "0000";
shared variable: count1 : integer := 0;
signal clk1: std_logic := '0';
signal data_in1 : std_logic_vector(14 downto 0) := "001111111111111";
begin
clk1 <= not clk1 after 1 ns; -- I needed this since I don't have the inputs you have...
-- comparison process
process(clk1, data_in, rst)
begin
for i in 0 to 14
loop
if(data_in(i) = sync_word(i)) then
count1 <= count1 + 1;
end if;
end loop;
correlation <= std_logic_vector(to_unsigned(count1,4));
count := 0;
end process;
end behave;
I am not sure, if this will help you, but I hope so. Especially, it is important to use a variable for counting, I think, so you just have to transform the format into std_logic_vector, the instruction "to_unsigned" is within numeric_std.
All you have to realize is to connect the data_in with the internal signal data_in1 and you can compare any data_in with sync_word.
greetings, burn
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burn77 |
05.10.04, 13:18 |
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Re: StateCAD
Den Guide hast Du? :confused:
toolbox.xilinx.com/docsan/xilinx4/pdf/docs/stc/stc.pdf
bzw. die online hilfe? :confused:
http://toolbox.xilinx.com/docsan/xilinx6/help/state/state.htm
ansonsten tut es mir leid :( , dass ich nicht weiter helfen konnte,
bis bald, gruß
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burn77 |
26.08.04, 09:28 |
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Re: StateCAD
Mit StateCAD kenne ich mich jetzt nicht aus :confused: , aber um direkt auf Dein Beispiel anzusprechen, wäre ich jetzt der Meinung, dass es eigentlich recht einfach ist.
Vektor_dat ist das Register mit Bitanzahl 12
wenn Du jetzt das 7. Bit anschauen möchtest:
if (Vektor_dat(7) = '1') then
current_state := next_state;
end if;
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burn77 |
25.08.04, 08:39 |
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